I. Field
The present invention relates generally to electronics circuits, and more specifically to a phase-locked loop.
II. Background
A phase-locked loop (PLL) is a circuit that receives a reference signal having a reference frequency and generates an output signal having an output frequency that is related to the reference frequency. A PLL is often used when an accurate output frequency is needed. The reference frequency is typically a precise frequency. The output frequency has similar accuracy as the reference frequency but may be many times higher than the reference frequency.
A PLL typically includes a voltage controlled oscillator (VCO) that generates a VCO signal, a loop filter that generates a control voltage for the VCO, and other supporting circuit blocks. The operation of the PLL may be divided into two parts —an acquisition phase and a tracking phase. In the acquisition phase, the PLL attempts to lock the frequency of the VCO signal to the frequency of the reference signal. In the tracking phase, which commences after successfully completing acquisition, the PLL adjusts the frequency/phase of the VCO signal to track variations in the frequency/phase of the reference signal.
The performance of the acquisition and tracking phases is determined by various factors including the characteristics of the VCO and loop filter. When the PLL is first powered up, the control voltage from the loop filter typically starts at a voltage rail, and there may be a large initial frequency error between the VCO signal and the reference signal. The feedback mechanism of the PLL may be relied upon to adjust the control voltage to lock the VCO frequency to the reference frequency. However, if the VCO has a wide frequency range and/or if the closed-loop bandwidth of the PLL is small relative to the initial frequency error, then acquisition may take a long time or may never be achieved.
There is therefore a need in the art for techniques to quickly and reliably lock a VCO to a reference signal.